By Kerry Bernstein
Industry call for for microprocessor functionality has stimulated persevered scaling of CMOS via a succession of lithography generations. Quantum mechanical obstacles to endured scaling are changing into with ease obvious. partly Depleted Silicon-on-Insulator (PD-SOI) know-how is rising as a promising technique of addressing those boundaries. It additionally introduces extra layout complexity which has to be good understood. SOI Circuit layout suggestions first introduces the scholar or practicing engineer to SOI equipment physics and its basic idiosyncrasies. It then walks the reader via realizations of those mechanisms that are saw in universal high-speed microprocessor designs. ideas of thumb and comparisons to traditional bulk CMOS are provided to steer implementation. SOI's final virtue, in spite of the fact that, could lie within the specified circuit topologies it helps; a couple of those novel new ways can be defined. SOI Circuit layout options attracts upon the most recent undefined literature in addition to the firsthand reviews of its authors. it truly is a great advent to the thoughts of governing SOI use and presents an organization origin for extra research of this interesting new know-how paradigm.
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Additional resources for SOI Circuit Design Concepts
However, it requires the use of a “triple well” process and much more space than SOI. In a more traditional twin well CMOS process on an p-type substrate, the body’s of the PFETs are controllable by controlling the potential of each respective NWELL. There is no control of the body of an individual NFET since they share the common substrate which is usually grounded. In a partially depleted SOI CMOS FET structure, there is a conducting path beneath the FET that can be used to control the potential of the body.
8 Body contacts for a partially depleted NFET. the gate is a T-shape. A p+ region is created at the crossbar of the T-shaped gate. This p+ region is connected to the body of the NFET through the p-type region directly under the gate. Here, the body is a unique terminal and needs to be contacted with an 22 SOI Circuit Design Concepts Transistor Structures interconnect and a via at the body contact to control the potential of the body. One consequence of the T-shaped connection is that the width of the NFET is now increased by a long channel length device that connects the source and drain under the crossbar portion of the gate.
3. 2]. In addition to the damage at the silicon interface, impact ionization of silicon lattice atoms leaves behind positive charge, which accumulates in the isolated body of the device, and electrons, collected at the drain or gate regions. The high energy tail of the majority carrier energy distribution has the capability of ionizing atoms at the pinched-off (drain) end of the channel. 4 schematically illustrates this process. e. drain at voltage VDD and source grounded for an NFET) but the gate voltage is less than VT.