By Keh-La Lin, Armin Kemna, Bedrich J. Hosticka
One of the most traits of microelectronics is towards layout for built-in structures, i.e., system-on-a-chip (SoC) or system-on-silicon (SoS). because of this improvement, layout recommendations for mixed-signal circuits turn into extra vital than prior to. between different units, analog-to-digital and digital-to-analog converters are the 2 bridges among the analog and the electronic worlds. along with, low-power layout procedure is among the major matters for embedded platforms, specifically for handheld applications.
Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems goals at layout suggestions for low-power, high-speed analog-to-digital converter processed via the normal CMOS expertise. also this ebook covers actual integration problems with A/D converter built-in in SoC, i.e., substrate crosstalk and reference voltage community layout.
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Extra info for Modular low-power, high-speed CMOS analog-to-digital converter of embedded systems
2 The Loop Filter The design of the loop filter determines most of the specifications of the PLL. Extra poles and zeros in the loop transfer function influence the noise and dynamic performance of the loop. In the previous section, the first-order loop is already discussed. From Eq. 18), it is clear that good tracking and narrow loop bandwidth are incompatible for the first-order PLL; Therefore it is not often used. In what follows the first-order loop is extended to higher orders and types to improve the PLL performance.
The constraint of an odd number of inverter poses a limit on the highest output frequency, since at least three inverters are necessary to realize oscillation. e. differential pairs) with cross-coupled connections allow the use of only two inverters in the ring. The higher circuit complexity limits the speed enhancement of these topologies. To enhance the high frequency operation and to increase the tuning range, a topology with dual-delay paths is developed in [Park99]; A negative skewed delay path decreases the unit delay in the ring and by combining the negative skewed delay and the normal delay path, the frequency range is increased.
The noise from the reference is low-passed to the PLL output with the same cross-over frequency, but within the PLL band the noise is amplified by the division factor, N. The resulting phase noise spectra are depicted in Fig. 6 (b). The reference noise exhibits the same three region as the VCO noise, but with a much smaller magnitude. This noise can corrupt the PLL output phase noise, since it is amplified by N for frequencies below Noise from other building blocks in the PLL is also low-passed towards the output with a gain depending on their position in the loop.